1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

library IEEE;
use IEEE.std_logic_1164.all;
entity SINTRANSITO is
    port (B3, B2, B1, B0: in BIT; VM, AM, VD: out BIT);
end SINTRANSITO;
architecture SINALT of SINTRANSITO is
signal vermelho, amarelo, verde: BIT;
begin
    VM <= vermelho;
    AM <= amarelo;
    VD <= verde;
    process (B3, B2, B1)
    begin
        verde <= B2;
        amarelo <= (not B2) and (B3 xor B1);
        vermelho <= (not B2) and ((not B3) or B1);
    end process;
end SINALT;